 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ? 1 ? e02301a2x-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD3423GA 96 pin lflga (plastic) description the CXD3423GA is a timing generator and ccd signal processor ic for the icx284, icx432/434 ccd image sensor. features ? timing generator functions horizontal drive frequency 18 to 24.3mhz (base oscillation frequency 36 to 48.6mhz) supports frame readout/draft (sextuple speed)/ af (auto focus drive) (icx432 mode) supports frame readout/draft (quadruple speed)/ af (auto focus drive) (icx434 mode) high-speed/low-speed shutter function horizontal and vertical drivers for ccd image sensor ccd signal processor functions correlated double sampling programmable gain amplifier (pga) allows gain adjustment over a wide range (?6 to +42db) 12-bit a/d converter chip scale package (csp): csp allows vast reduction in the ccd camera block footprint applications digital still cameras applicable ccd image sensors icx284 (type 1/2.7, 2020k pixels) icx432 (type 1/2.7, 3240k pixels) icx434 (type 1/3.2, 2020k pixels) timing generator and signal processor for frame readout ccd image sensor absolute maximum ratings supply voltage v dd a, v dd b, v dd c, v dd dv ss ? 0.3 to +7.0 v v dd e, v dd f, v dd gv ss ? 0.3 to +4.0 v vl ?10.0 to v ss v vh vl ? 0.3 to +26.0 v input voltage (analog) v in v ss ? 0.3 to v dd + 0.3 v input voltage (digital) v i v ss ? 0.3 to v dd + 0.3 v output voltage v o1 v ss ? 0.3 to v dd + 0.3 v v o2 vl ? 0.3 to v ss + 0.3 v v o3 vl ? 0.3 to vh + 0.3 v operating temperature topr ?20 to +75 c storage temperature tstg ?55 to +125 c recommended operating conditions supply voltage v dd a, v dd b, v dd c, v dd d, v dd e, v dd f, v dd g 3.0 to 3.6 v vm 0.0 v vh 14.5 to 15.5 v vl ?7.0 to ?8.0 v operating temperature topr ?20 to +75 c
? 2 ? CXD3423GA block diagram c7 c3 d8 c2 d7 c1 b8 av dd3 b6 av dd4 b9 av ss3 a6 av ss4 c5 av ss5 a3 sck2 a4 ssi2 b4 sen2 a5 test3 c4 test4 b5 test5 e2 dv dd1 f2 dv ss3 f3 dv dd2 e3 dv ss1 f1 b3 dv ss2 d0 (lsb) latch serial port register dac pga cds adc preblanking dummy pixel auto zero pulse generator v driver serial port register black level auto zero b2 d1 b1 d2 c3 d3 c2 d4 c1 d5 d3 d6 d2 d7 d1 d8 e1 d9 g1 adclki g2 clpobi g3 clpdmi h1 adclk h2 clpob h3 clpdm j3 v ss4 l1 osci k1 osco j1 cki j2 cko k2 mcko n8 sncsl l2 ssi1 m6 vl m3 vm l5 vh m9 wen/fld n9 id/exp j7 v ss3 j9 h2 j8 h1 h9 v dd3 k9 v ss2 k8 rg k7 v dd2 h8 v dd4 g7 pblk g8 xshd g9 xshp f7 pblki f8 xshdi e7 av ss2 f9 xshpi d9 av ss1 e8 av dd2 e9 av dd1 c9 ccdin c6 c9 a7 c8 b7 c7 a8 av ss6 a9 av dd5 c8 c4 m1 sck1 n1 sen1 n3 v ss5 l7 v ss1 k3 v dd5 l9 v dd1 m2 vd n2 hd n4 v5a/v3a n6 v3b/v1b l6 v3a/v1a v2/nc m4 v1/nc n5 m5 v5b/v3b m8 rst l3 test2 h7 test1 l8 ssgsl l4 v4/v2 n7 v6/v4 m7 sub 1/2 latch selector selector ssg a1 a2 d11 (msb) d10 ? 3 ? CXD3423GA pin configuration (top view) note) the symbol in parenthesis is for icx434 mode. d1 d4 d7 d10 d11 dv ss2 adclki adclk cki osco osci sck1 sen1 a b c d e f g h j k l m n d0 d3 d6 d9 dv dd1 dv ss3 clpobi clpob cko mcko ssi1 vd hd sck2 d2 d5 d8 dv ss1 dv dd2 clpdmi clpdm v ss4 v dd5 test2 vm v ss5 ssi2 sen2 test4 v4 (v2) v2 (nc) v5a (v3a) test3 test5 av ss5 vh v5b (v3b) v1 (nc) av ss4 av dd4 c9 v3a (v1a) vl v3b (v1b) c8 c7 c3 c1 av ss2 pblki pblk test1 v ss3 v dd2 v ss1 sub v6 (v4) av ss6 av dd3 c4 c2 av dd2 xshdi xshd v dd4 h1 rg ssgsl rst sncsl av dd5 av ss3 ccdin av ss1 av dd1 xshpi xshp v dd3 h2 v ss2 v dd1 wen/fld id/exp 12345 6789 ? 4 ? CXD3423GA pin description pin no. a1 a2 a3 a4 a5 a6 a7 a8 a9 b1 b2 b3 b4 b5 b6 b7 b8 b9 c1 c2 c3 c4 c5 c6 c7 c8 c9 d1 d2 d3 d7 d8 d9 e1 e2 e3 e7 symbol d1 d0 sck2 ssi2 test3 av ss4 c8 av ss6 av dd5 d4 d3 d2 sen2 test5 av dd4 c7 av dd3 av ss3 d7 d6 d5 test4 av ss5 c9 c3 c4 ccdin d10 d9 d8 c1 c2 av ss1 d11 dv dd1 dv ss1 av ss2 i/o o o i i i ? ? ? ? o o o i i ? ? ? ? o o o i ? ? ? ? i o o o ? ? ? o ? ? ? description adc output. adc output (lsb). ccd signal processor block serial interface clock input. (schmitt trigger) ccd signal processor block serial interface data input. (schmitt trigger) ccd signal processor block test input 3. connect to dv ss . ccd signal processor block analog gnd. capacitor connection. ccd signal processor block analog gnd. ccd signal processor block analog power supply. adc output. adc output. adc output. ccd signal processor block serial interface enable input. (schmitt trigger) ccd signal processor block test input 5. connect to dv dd . ccd signal processor block analog power supply. capacitor connection. ccd signal processor block analog power supply. ccd signal processor block analog gnd. adc output. adc output. adc output. ccd signal processor block test input 4. connect to dv ss . ccd signal processor block analog gnd. capacitor connection. capacitor connection. capacitor connection. ccd output signal input. adc output. adc output. adc output. capacitor connection. capacitor connection. ccd signal processor block analog gnd. adc output (msb). ccd signal processor block digital power supply. (power supply for adc) ccd signal processor block digital gnd. (gnd for adc) ccd signal processor block analog gnd. ? 5 ? CXD3423GA pin no. e8 e9 f1 f2 f3 f7 f8 f9 g1 g2 g3 g7 g8 g9 h1 h2 h3 h7 h8 h9 j1 j2 j3 j7 j8 j9 k1 k2 k3 k7 k8 k9 l1 l2 symbol av dd2 av dd1 dv ss2 dv ss3 dv dd2 pblki xshdi xshpi adclki clpobi clpdmi pblk xshd xshp adclk clpob clpdm test1 v dd4 v dd3 cki cko v ss4 v ss3 h1 h2 osco mcko v dd5 v dd2 rg v ss2 osci ssi1 i/o ? ? ? ? ? i i i i i i o o o o o o i ? ? i o ? ? o o o o ? ? o ? i i description ccd signal processor block analog power supply. ccd signal processor block analog power supply. ccd signal processor block digital gnd. ccd signal processor block digital gnd. ccd signal processor block digital power supply. pulse input for horizontal and vertical blanking period pulse cleaning. (schmitt trigger) ccd data level sample-and-hold pulse input. (schmitt trigger) ccd precharge level sample-and-hold pulse input. (schmitt trigger) clock input for analog/digital conversion. (schmitt trigger) ccd optical black signal clamp pulse input. (schmitt trigger) ccd dummy signal clamp pulse input. (schmitt trigger) pulse output for horizontal and vertical blanking period pulse cleaning. ccd data level sample-and-hold pulse output. ccd precharge level sample-and-hold pulse output. clock output for analog/digital conversion. logical phase adjustment possible using the serial interface data. ccd optical black signal clamp pulse output. horizontal and vertical ob pattern charge possible using the serial interface data. ccd dummy signal clamp pulse output. timing generator block test input 1. normally fix to gnd. (with pull-down resistor) timing generator block digital power supply. (power supply for cds block) timing generator block digital power supply. (power supply for h1/h2) inverter input. inverter output. timing generator block digital gnd. timing generator block digital gnd. ccd horizontal register clock output. ccd horizontal register clock output. inverter output for oscillation. when not used, leave open or connect a capacitor. system clock output for signal processor ic. timing generator block digital power supply. (power supply for common logic block) timing generator block digital power supply. (power supply for rg) ccd reset gate pulse output. timing generator block digital gnd. inverter input for oscillation. when not used, fix to low. timing generator block serial interface data input. schmitt trigger input. ? 6 ? CXD3423GA pin no. l3 l4 l5 l6 l7 l8 l9 m1 m2 m3 m4 m5 m6 m7 m8 m9 n1 n2 n3 n4 n5 n6 n7 n8 n9 symbol test2 v4 (v2) vh v3a (v1a) v ss1 ssgsl v dd1 sck1 vd vm v2 (nc) v5b (v3b) vl sub rst wen/fld sen1 hd v ss5 v5a (v3a) v1 (nc) v3b (v1b) v6 (v4) sncsl id/exp i/o i o ? o ? i ? i i/o ? o o ? o i o i i/o ? o o o o i o description timing generator block test input 2. normally fix to gnd. (with pull-down resistor) ccd vertical register clock output. the symbol in parenthesis is for icx434 mode. timing generator block 15.0v power supply. (power supply for vertical driver) ccd vertical register clock output. the symbol in parenthesis is for icx434 mode. timing generator block digital gnd. internal ssg enable. high: internal ssg valid, low: external sync valid (with pull-down resistor) timing generator block digital power supply. (power supply for common logic block) timing generator block serial interface clock input. schmitt trigger input. vertical sync signal input/output. timing generator block gnd. (gnd for vertical driver) ccd vertical register clock output. the symbol in parenthesis is for icx434 mode. ccd vertical register clock output. the symbol in parenthesis is for icx434 mode. timing generator block ?7.5v power supply. (power supply for vertical driver) ccd electric shutter pulse. timing generator block reset input. high: normal operation, low: reset control normally apply reset during power-on. schmitt trigger input. memory write timing pulse output/field discrimination pulse output. switching possible using the serial interface data. (default: wen output) timing generator block serial interface strobe input. schmitt trigger input. horizontal sync signal input/output. timing generator block digital gnd. ccd vertical register clock output. the symbol in parenthesis is for icx434 mode. ccd vertical register clock output. the symbol in parenthesis is for icx434 mode. ccd vertical register clock output. the symbol in parenthesis is for icx434 mode. ccd vertical register clock output. the symbol in parenthesis is for icx434 mode. control input used to switch sync system. high: cki sync, low: mcko sync (with pull-down resistor) vertical direction line identification pulse output/exposure time identification pulse output. switching possible using the serial interface data. (default: id output) ? 7 ? CXD3423GA electrical characteristics timing generator block electrical characteristics dc characteristics (within the recommended operating conditions) item pins symbol conditions min. typ. max. unit supply voltage 1 supply voltage 2 supply voltage 3 supply voltage 4 input voltage 1 ? 1 input voltage 2 ? 2 input/output voltage output voltage 1 output voltage 2 output voltage 3 output voltage 4 output voltage 5 output voltage 6 output current 1 output current 2 v dd2 v dd3 v dd4 v dd1 , v dd5 rst, ssi1, sck1, sen1 test1, test2, sncsl, ssgsl vd, hd h1, h2 rg xshp, xshd, pblk, clpob, clpdm, adclk cko mcko id/exp, wen/fld v1, v2, v3a, v3b, v4, v5a, v5b, v6 sub feed current where i oh = ?1.2ma pull-in current where i ol = 2.4ma feed current where i oh = ?14.0ma pull-in current where i ol = 9.6ma feed current where i oh = ?3.3ma pull-in current where i ol = 2.4ma feed current where i oh = ?3.3ma pull-in current where i ol = 2.4ma feed current where i oh = ?6.9ma pull-in current where i ol = 4.8ma feed current where i oh = ?3.3ma pull-in current where i ol = 2.4ma feed current where i oh = ?2.4ma pull-in current where i ol = 4.8ma v1, v2, v3a/b, v4, v5a/b, v6 = ?8.25v v1, v2, v3a/b, v4, v5a/b, v6 = ?0.25v v1, v3a/b, v5a/b = 0.25v v1, v3a/b, v5a/b = 14.75v sub = ?8.25v sub = 14.75v 3.0 3.0 3.0 3.0 0.8v dd d 0.7v dd d 0.8v dd d v dd d ? 0.8 v dd b ? 0.8 v dd a ? 0.8 v dd c ? 0.8 v dd d ? 0.8 v dd d ? 0.8 v dd d ? 0.8 10.0 5.0 5.4 3.3 3.3 3.3 3.3 3.6 3.6 3.6 3.6 0.2v dd d 0.3v dd d 0.2v dd d 0.4 0.4 0.4 0.4 0.4 0.4 0.4 ?5.0 ?7.2 ?4.0 v v v v v v v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma ? 1 this input pin is a schmitt trigger input. ? 2 these input pins are with pull-down resistor in the ic. note) the above table indicates the condition for 3.3v drive. v dd a v dd b v dd c v dd d v i+ v i? v ih1 v il1 v ih2 v il2 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh4 v ol4 v oh5 v ol5 v oh6 v ol6 v oh7 v ol7 i ol i om1 i om2 i oh i osl i osh ? 8 ? CXD3423GA inverter i/o characteristics for oscillation (within the recommended operating conditions) item logical vth input voltage output voltage feedback resistor oscillation frequency pins osci osci osco osci, osco osci, osco symbol lvth v ih v il v oh v ol rfb f conditions feed current where i oh = ?3.6ma pull-in current where i ol = 2.4ma v in = v dd d or v ss min. 0.7v dd d v dd d ? 0.8 500k 20 ty p. v dd d/2 2m max. 0.3v dd d 0.4 5m 50 unit v v v v v ? mhz inverter input characteristics for base oscillation clock duty adjustment (within the recommended operating conditions) item logical vth input voltage input amplitude cki symbol lvth v ih v il v in conditions fmax 50mhz sine wave min. 0.7v dd d 0.3 ty p. v dd d/2 max. 0.3v dd d unit v v v vp-p note) input voltage is the input voltage characteristics for direct input from an external source. input amplitude is the input amplitude characteristics in the case of input through a capacitor. switching characteristics (vh = 15.0v, vm = gnd, vl = ?7.5v) item rise time fall time output noise voltage symbol ttlm ttmh ttlh ttml tthm tthl vclh vcll vcmh vcml conditions vl to vm vm to vh vl to vh vm to vl vh to vm vh to vl min. 200 200 30 200 200 30 ty p. 350 350 60 350 350 60 max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 unit ns ns ns ns ns ns v v v v notes) 1. the mos structure of this ic has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. for noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1f or more) between each power supply pin (vh, vl) and gnd. 3. to protect the ccd image sensor, clamp the sub pin output at vh before input to the ccd image sensor. pins ? 9 ? CXD3423GA switching waveforms waveform noise vcmh vcml vm vl vclh vcll v1 (v3a, v3b, v5a, v5b) v2 (v4, v6) sub ttmh tthm vh vm vl vm vl vh vl 90% 10% 90% 10% ttlm ttlm 90% 10% 90% 10% ttlh tthl 90% 90% 10% 10% ttml 90% 10% ttml 90% 10% ? 10 ? CXD3423GA measurement circuit c1 3300pf c2 560pf c3 820pf c4 8pf c5 180pf c6 10pf r1 30 ? r2 10 ? serial interface data n1 n2 n3 n4 n6 m7 l7 n8 n9 m1 m2 m3 m4 m5 l6 l4 n3 l2 k2 k9 k8 k7 k1 l1 k3 j9 j8 j7 j3 j2 j1 h9 h8 h7 h3 h2 l3 g9 g8 g7 a2 a1 a3 a4 a5 a6 a7 a8 a9 b1 b2 b3 b4 b5 b6 b7 b9 b8 c1 c2 c3 c4 c5 c6 l5 m6 n7 l8 l9 l3 m8 m9 e8 d8 d7 d3 d2 d1 c9 c8 c7 f3 f2 g1 e9 d9 e7 g3 g2 h1 f9 f8 f7 f1 e3 e2 vd CXD3423GA v4 e1 d11 vh vl v6 ssgsl v dd1 sck1 vd vm v2 v5b v3a test2 rst wen/fld sen1 hd vm v5a v3b sub v ss1 sncsl id/exp n5 v1 clpdmi clpobi adclk xshpi xshdi pblki dv dd2 dv ss3 adclki av dd1 av ss1 av ss2 dv ss2 dv ss1 dv dd1 av dd2 c2 c1 d8 d9 d10 ccdin c4 c3 v ss5 ssi1 mcko v ss2 rg v dd2 osco osci v dd5 h2 h1 v ss3 v ss4 cko cki v dd3 v dd4 test1 clpdm clpob v ss4 xshp xshd pblk d0 d1 sck2 ssi2 test3 av ss4 c8 av ss6 av dd5 d4 d3 d2 sen2 test5 av dd4 c7 av ss3 av dd3 d7 d6 d5 test4 av ss5 c9 hd +3.3v +15.0v ?7.5v c3 cki c6 c4 c5 c5 c6 c2 c2 c2 c2 c2 r1 r1 r1 r2 r1 r1 r1 c2 c2 c2 c2 c2 c2 c2 c2 c2 c1 c1 c1 c1 c1 c1 c2 ? 11 ? CXD3423GA ac characteristics ac characteristics between the serial interface clocks serial interface clock internal loading characteristics (1) ? be sure to maintain a constantly high sen1 logic level near the falling edge of the hd in the horizontal period during which v1, v3a/b and v5a/b values take the ternary value and during that horizontal period. (within the recommended operating conditions) ssi1 0.2v dd d 0.2v dd d 0.8v dd d ts2 th1 ts1 ts3 0.8v dd d 0.8v dd d sck1 sen1 sen1 th1 enlarged view example: during frame mode 0.2v dd d ts1 0.2v dd d v1, v3a/b, v5a/b vd hd hd v1, v3a/b, v5a/b sen1 0.8v dd d (within the recommended operating conditions) symbol ts1 th1 definition sen1 setup time, activated by the falling edge of hd sen1 hold time, activated by the falling edge of hd min. 0 123 typ. max. unit ns s symbol ts1 th1 ts2 ts3 definition ssi1 setup time, activated by the rising edge of sck1 ssi1 hold time, activated by the rising edge of sck1 sck1 setup time, activated by the rising edge of sen1 sen1 setup time, activated by the rising edge of sck1 min. 20 20 20 20 typ. max. unit ns ns ns ns ? 12 ? CXD3423GA serial interface clock internal loading characteristics (2) ? be sure to maintain a constantly high sen1 logic level near the falling edge of vd. (within the recommended operating conditions) serial interface clock output variation characteristics normally, the serial interface data is loaded to the CXD3423GA at the timing shown in "serial interface clock internal loading characteristics (1)" above. however, one exception to this is when the data such as stb is loaded to the CXD3423GA and controlled at the rising edge of sen1. see "description of operation". (within the recommended operating conditions) th1 enlarged view 0.2v dd d ts1 0.2v dd d vd hd vd hd sen1 0.8v dd d example: during frame mode symbol ts1 th1 definition sen1 setup time, activated by the falling edge of vd sen1 hold time, activated by the falling edge of vd min. 0 200 typ. max. unit ns ns symbol tpdpulse definition output signal delay, activated by the rising edge of sen1 min. 5 typ. max. 100 unit ns 0.8v dd d sen1 output signal tpdpulse ? 13 ? CXD3423GA rst loading characteristics (within the recommended operating conditions) vd and hd loading characteristics mcko load capacitance = 10pf (within the recommended operating conditions) output variation characteristics wen/fld and id/exp load capacitance = 10pf (within the recommended operating conditions) rst 0.2v dd d tw1 0.8v dd d vd, hd mcko ts1 th1 0.2v dd d 0.8v dd d 0.2v dd d 0.8v dd d mcko wen/fld, id/exp tpd1 symbol tpd1 definition time until the above outputs change after the rise of mcko min. 20 typ. max. 60 unit ns symbol ts1 th1 definition vd and hd setup time, activated by the rising edge of mcko vd and hd hold time, activated by the rising edge of mcko min. 13 0 typ. max. unit ns ns symbol tw1 definition rst pulse width min. 35 typ. max. unit ns ? 14 ? CXD3423GA ccd signal processor block electrical characteristics dc characteristics (fc = 24.3msps, dv dd1, 2 = av dd1, 2, 3, 4, 5 = 3.3v, ta = 25c) item supply voltage 1 supply voltage 2 supply voltage 3 analog input capacitance input voltage a/d clock duty output voltage pins dv dd1 dv dd2 av dd1 , av dd2 , av dd3 , av dd4 , av dd5 ccdin sck2, ssi2, sen2, test3, test4, xshdi, xshpi, adclki, clpobi, clpdmi, pblki adclki d0 to d11 symbol v dd e v dd f v dd g c in v i+ v i? v oh v ol conditions feed current where i oh = ?2.0ma pull-in current where i ol = 2.0ma min. 3.0 3.0 3.0 v dd e ? 0.9 ty p. 3.3 3.3 3.3 15 1.8 1.1 50 max. 3.6 3.6 3.6 0.4 unit v v v pf v v % v v analog characteristics (fc = 24.3msps, dv dd1, 2 = av dd1, 2, 3, 4, 5 = 3.3v, ta = 25c) item ccdin input voltage amplitude pga maximum gain pga minimum gain adc resolution adc maximum conversion rate adc integral non-linearity error adc differential non-linearity error signal-to-noise ratio ccdin input voltage clamp level ccd optical black signal clamp level pins v in gmax gmin fc max e l e d snr clp ob conditions pga gain = 0db, output full scale pga gain setting data = "3ffh" pga gain setting data = "000h" pga gain = 0db pga gain = 0db pga gain = 0db oblvl = "8h" pga gain = 0db min. 900 24.3 ty p. 42 ?6 12 2.0 1.0 77 1.5 130 max. 1100 unit mv db db bit mhz lsb lsb db v lsb ? 15 ? CXD3423GA ac characteristics ac characteristics between the serial interface clocks ? the setting values are reflected to the operation 6 adclki clocks after the serial data is loaded at the rise of sen2. (fc = 24.3msps, dv dd1, 2 = av dd1, 2, 3, 4, 5 = 3.3v, ta = 25c) symbol tp1 ts1 th1 ts2 ts3 definition sck2 clock period ssi2 setup time, activated by the rise of sck2 ssi2 hold time, activated by the rise of sck2 sck2 setup time, activated by the rise of sen2 sen2 setup time, activated by the rise of sck2 min. 100 30 30 30 30 typ. max. unit ns ns ns ns ns ssi2 0.2v dd 0.2v dd 0.8v dd ts2 th1 ts1 ts3 0.8v dd 0.8v dd sck2 sen2 sen2 ? 16 ? CXD3423GA cds/adc timing chart ? set the input pulse polarity setting data d13, d14 and d15 of the serial interface data to "0". (fc = 24.3msps, dv dd1, 2 = av dd1, 2, 3, 4, 5 = 3.3v, ta = 25c) preblanking timing chart symbol tw1 dl definition adclki clock period adclki clock duty data latency min. 41 typ. max. unit ns % clocks 50 9 nn + 1 n ? 10 ccdin xshpi xshdi adclki d0 to d11 n ? 9 n ? 8 n ? 7 tw1 dl n + 2 n + 3 11 clocks 11 clocks pblki adclki d0 to d11 all "0" ? 17 ? CXD3423GA description of operation pulses output from the CXD3423GA's timing generator block are controlled mainly by the rst pin and by the serial interface data. the pin status table is shown below, and the details of serial interface control are described on page 19 and thereafter. pin status table pin no. symbol cam slp stb rst a1 a2 a3 a4 a5 a6 a7 a8 a9 b1 b2 b3 b4 b5 b6 b7 b8 b9 c1 c2 c3 c4 c5 c6 c7 c8 c9 d1 d2 d3 d7 d1 d0 sck2 ssi2 test3 av ss4 c8 av ss6 av dd5 d4 d3 d2 sen2 test5 av dd4 c7 av dd3 av ss3 d7 d6 d5 test4 av ss5 c9 c3 c4 ccdin d10 d9 d8 c1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pin no. symbol cam slp stb rst d8 d9 e1 e2 e3 e7 e8 e9 f1 f2 f3 f7 f8 f9 g1 g2 g3 g7 g8 g9 h1 h2 h3 h7 h8 h9 j1 j2 j3 j7 j8 c2 av ss1 d11 dv dd1 dv ss1 av ss2 av dd2 av dd1 dv ss2 dv ss3 dv dd2 pblki xshdi xshpi adclki clpobi clpdmi pblk xshd xshp adclk clpob clpdm test1 v dd4 v dd3 cki cko v ss4 v ss3 h1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? act l l h act l l act act l l act act l l act act l l h act l l h ? ? ? act act act act act act l act ? ? act l l act ? 18 ? CXD3423GA pin no. symbol cam slp stb rst j9 k1 k2 k3 k7 k8 k9 l1 l2 l3 l4 l5 l6 l7 l8 l9 m1 h2 osco mcko v dd5 v dd2 rg v ss2 osci ssi1 test2 v4 (v2) vh v3a (v1a) v ss1 ssgsl v dd1 sck1 act l l act act act act act act act l act ? ? act l l act ? act act act act act act act dis ? act vm vm vm ? act vh vh vm ? act act act act ? act act act dis pin no. symbol cam slp stb rst m2 m3 m4 m5 m6 m7 m8 m9 n1 n2 n3 n4 n5 n6 n7 n8 n9 vd ? 1 vm v2 (nc) v5b (v3b) vl sub rst wen/fld sen1 hd ? 1 v ss5 v5a (v3a) v1 (nc) v3b (v1b) v6 (v4) sncsl id/exp act l l h ? act vm vm vm act vh vh vl ? act vh vh vl act act act l act l l l act act act dis act l l h ? act vh vh vl act vh vh vm act vh vh vm act vh vh vl act act act act act l l l ? 1 it is for output. for input, all items are "act". note) act means that the circuit is operating, and dis means that loading is stopped. l indicates a low output level, and h a high output level in the controlled status. also, vh, vm and vl indicate the voltage levels applied to vh (pin l5), vm (pin m3) and vl (pin m6), respectively, in the controlled status. ? 19 ? CXD3423GA timing generator block serial interface control the CXD3423GA's timing generator block basically loads and reflects the timing generator block serial interface data sent in the following format in the readout portion at the falling edge of hd. here, readout portion specifies the horizontal period during which v3a/b and v5a/b, etc. take the ternary value. note that some items reflect the timing generator block serial interface data at the falling edge of vd or the rising edge of sen1. there are two categories of timing generator block serial interface data: CXD3423GA timing generator block drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). the details of each data are described below. 00 01 02 03 04 05 06 07 41 42 43 44 45 46 47 ssi1 sck1 sen1 ? 20 ? CXD3423GA data d00 to d07 d08 d09 to d11 d12, d13 d14, d15 d16 d17 d18, d19 d20 d21 d22 to d30 d31 d32 d33 d34, d35 d36, d37 d38, d39 d40 to d47 symbol chip ctg ? mode ? ntpl ccd ? smd htsg ? fld fgob exp ptob ldad stb ? function chip enable category switching ? drive mode switching ? internal ssg function switching ? 1 ccd switching ? 1 ? electronic shutter mode switching ? 2 htsg control switching ? 2 ? wen/fld output switching wide clpob generation switching id/exp output switching clpob waveform pattern switching adclk logic phase adjustment standby control ? data = 0 data = 1 10000001 enabled other values disabled see d08 ctg. ?? see d12 , d13 mode. ?? ntsc pal icx432 icx284/434 ?? off on off on ?? wen fld fl off on id exp see d34 , d35 ptob. see d36 , d37 ldad. see d38 , d39 stb. ?? control data rst all 0 0 all 0 0 0 0 0 0 0 0 all 0 0 0 0 all 0 all 0 all 0 all 0 ? 1 see d12 , d13 mode. ? 2 see d20 smd. ? 21 ? CXD3423GA data d00 to d07 d08 d09 d10 to d19 d20 to d31 d32 to d41 d42 to d47 symbol chip ctg ? svd shd spl ? function chip enable category switching ? electronic shutter vertical period specification electronic shutter horizontal period specification high-speed shutter position specification ? data = 0 data = 1 10000001 enabled other values disabled see d08 ctg. ? see d10 to d19 svd. see d20 to d31 shd. see d32 to d41 spl. ? shutter data rst all 0 0 0 all 0 all 0 all 0 all 0 ? 22 ? CXD3423GA detailed description of each data shared data: d08 ctg [category] of the data provided to the CXD3423GA by the timing generator block serial interface, the CXD3423GA loads d10 and subsequent data to each data register as shown in the table below according to d08 . note that the CXD3423GA can apply these categories consecutively within the same vertical period. however, care should be taken as the data is overwritten if the same category is applied. control data: d12 , d13 mode [drive mode] the CXD3423GA drive mode can be switched as follows. however, the drive mode bits are loaded to the CXD3423GA and reflected at the falling edge of vd. ? 1 the test mode results in icx284/434 mode. draft mode is the pulse elimination drive mode. this is a high frame rate drive mode that can be used for purposes such as monitoring and moving pictures. af mode is the drive mode for applications with an even higher frame rate, and is used for auto focus (af). frame mode is the drive mode in which the data for all lines of the icx284/432/434 are read. control data: d16 ntpl [ssg function switching] the CXD3423GA internal ssg output pattern can be switched as follows. however, the drive mode bits are loaded to the CXD3423GA and reflected at the falling edge of vd. the default is "ntsc". d16 0 1 description of operation ntsc equivalent pattern output (internal ssg) pal equivalent pattern output (internal ssg) d13 0 0 1 1 d12 0 1 0 1 description of operation draft mode (default) frame mode af mode ? 1 test mode d08 0 1 description of operation loading to control data register loading to shutter data register ? 23 ? CXD3423GA control data: d38 , d39 stb [standby] the operating mode is switched as follows. however, the standby bits are loaded to the CXD3423GA and control is applied immediately at the rising edge of sen1. see the pin status table for the pin status in each mode. d39 x 0 1 d38 0 1 1 operating mode normal operating mode sleep mode standby mode symbol cam slp stb control data: d36 , d37 ldad [adclk logic phase] this indicates the adclk logic phase adjustment data. the default is "90" relative to mcko. d37 0 0 1 1 d36 0 1 0 1 degree of adjustment () 0 90 180 270 control data: d34 , d35 ptob [clpob waveform pattern] this indicates the clpob waveform pattern. the default is "normal". d35 0 0 1 1 d34 0 1 0 1 waveform pattern (normal) (shifted rearward) (shifted forward) (wide) control data: d32 fgob [wide clpob generation] this controls wide clpob generation during the vertical opb period. see the timing charts for the actual operation. the default is "off". d32 0 1 description of operation wide clpob generation off wide clpob generation on control data: d17 ccd [used ccd switching] this specifies the ccd image sensor to be used. however, like the drive mode bits, the ccd switching bits are loaded to the CXD3423GA and reflected at the falling edge of vd. the default is "icx432". d17 0 1 description of operation icx432 icx284/434 ? 24 ? CXD3423GA control data/shutter data: [electronic shutter] the CXD3423GA realizes various electronic shutter functions by using control data d20 smd and d21 htsg and shutter data d10 to d19 svd, d20 to d31 shd and d32 to d41 spl. these functions are described in detail below. first, the various modes are shown below. these modes are switched using control data d20 smd. the electronic shutter data is expressed as shown in the table below using d20 to d31 shd as an example. however, msb (d31) is a reserve bit for the future specification, and it is handled as a dummy on this ic. [electronic shutter stopped mode] during this mode, all shutter data items are invalid. sub is not output in this mode, so the shutter speed is the accumulation time for one field. [high-speed/low-speed shutter mode] during this mode, the shutter data items have the following meanings. note) the bit data definition area is assured in terms of the CXD3423GA functions, and does not assure the ccd characteristics. the period during which svd and shd are specified together is the shutter speed. an image of the exposure time calculation formula is shown below. in actual operation, the precise exposure time is calculated from the operating frequency, vd and hd periods, decoding value during the horizontal period, and other factors. (exposure time) = svd (1v period) + {(number of hd per 1v) ? (shd + 1)} (1h period) + (distance from sub to sg during the readout period) concretely, when specifying high-speed shutter, svd is set to "000h". (see the figure.) during low-speed shutter, or in other words when svd is set to "001h" or higher, the serial interface data is not loaded until this period is finished. the vertical period indicated here corresponds to one field in each drive mode. in addition, the number of horizontal periods applied to shd can be considered as (number of sub pulses ? 1). msb d31 x d30 0 d29 0 d28 1 d27 1 d26 1 d25 0 d24 0 lsb 1 c shd is expressed as 1c3h . d23 0 d22 0 d21 1 d20 1 3 d20 0 1 description of operation electronic shutter stopped mode electronic shutter mode symbol svd shd spl data d10 to d19 d20 to d31 d32 to d41 description number of vertical periods specification (000h svd 3ffh) number of horizontal periods specification (000h shd 7ffh) vertical period specification for high-speed shutter operation (000h spl 3ffh) ? 25 ? CXD3423GA further, spl can be used during this mode to specify the sub output at the desired vertical period during the low-speed shutter period. in the case below, sub is output based on shd at the spl vertical period out of (svd + 1) vertical periods. incidentally, spl is counted as "000h", "001h", "002h" and so on in conformance with svd. using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa. 01 01 002h 000h 10fh 050h vd shd v1a sub wen smd svd shd svd exp exposure time 11 001h 000h 002h 000h vd shd 000 001 002 v1a sub wen smd spl svd 10fh 0a3h shd svd exp exposure time spl ? 26 ? CXD3423GA [htsg control mode] this mode controls the ternary level outputs of v1, v3a/b, v5a/b (readout pulse block) using d21 htsg. d21 0 1 description of operation readout pulse (sg) normal operation htsg control mode [exp pulse] the id/exp pin (pin n9) output can be switched between the id pulse or the exp pulse using d33 exp. the default is the "id" pulse. see the timing charts for the id pulse. the exp pulse indicates the exposure time when it is high. in principle, the transition points are the last sub pulse falling edge and the readout pulse falling edge, that is to say from the time the charge is completely discharged until transfer ends. however, when the readout pulse timing differs within the same readout portion such as in draft mode, the average value is used. then, when there is no sub pulse in the next field, the readout pulse falling edge is defined as the start position, but in this case the transition points overlap and disappear, so a tentative start position is defined. this is shown below. 10 0 0 1 1 vd v1a sub vck wen htsg smd exp exposure time see the exp pulse indicated in the explanatory diagrams under [electronic shutter] for an image of operation. [icx432] [icx284/ 434] frame mode draft/af mode frame mode draft mode sg 1460 1682 a: 1071 b: 1175 1123 tentative start position 1480 1784 1091 1195 1175 ? 27 ? CXD3423GA chart-a1 vertical direction timing chart mode frame mode applicable ccd image sensor icx432 ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. in this drive mode, id is reset to (high, low, low) in the horizontal periods of each readout portion (a, b, c). ? wen/fld of this chart shows wen. ? the shaded portion of clpob shows the range over which the wide clpob can be set by the serial interface data. ? vd of this chart is indicated in ntsc equivalent pattern 587h (1h: 2760ck) + 1500ck units. for pal equivalent pattern, it is 70 4h + 960ck units. 11 1 c field a field b field 1548 1545 1236 9 6 3 8 5 2 1550 1547 8 5 2 7 4 1 4 1 6 3 vd sub hd v1 v2 v3a v3b v4 v5b v5a v6 ccd out pblk clpob wen/fld id/exp clpdm 1549 1546 588 588 564 588 565 564 43 43 43 high-speed sweep block high-speed sweep block high-speed sweep block [b] [a] [d] [c] ? 28 ? CXD3423GA chart-a2 vertical direction timing chart mode draft mode applicable ccd image sensor icx432 ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. in this drive mode, id is reset to low in the horizontal periods of each readout portion (e). ? wen/fld of this chart shows wen. ? the shaded portion of clpob shows the range over which the wide clpob can be set by the serial interface data. ? vd of this chart is indicated in ntsc equivalent pattern 269h (1h: 3004ck) + 2734ck units. for pal equivalent pattern, it is 32 3h + 1708ck units. [e] 1 1 [e] 1534 1541 1546 4 1 8 13 20 25 28 1544 1537 1532 1525 1546 1541 1534 1527 1549 6 5 10 17 22 29 30 4 1 8 13 20 25 28 6 5 10 17 22 29 30 vd sub hd v5a v3b v3a v2 v1 v5b v4 v6 ccd out pblk clpob wen/fld id/exp clpdm 1544 1537 1532 1549 270 263 270 263 3 3 ? 29 ? CXD3423GA chart-a3 vertical direction timing chart mode af mode applicable ccd image sensor icx432 ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. in this drive mode, id is reset to high in the horizontal periods of each readout portion (e). ? wen/fld of this chart shows wen. ? the shaded portion of clpob shows the range over which the wide clpob can be set by the serial interface data. ? vd of this chart is indicated in ntsc equivalent pattern 134h (1h: 3004ck) + 2869ck units. for pal equivalent pattern, it is 16 1h + 2356ck units. in addition, for pal equivalent pattern, the high-speed sweep block starts from 150h. 1 1 [e] [f] 1525 488 481 490 485 1527 46 4 6 vd sub hd v5a v3b v3a v2 v1 v5b v4 v6 ccd out pblk clpob wen/fld id/exp clpdm [g] [e] [f] [g] high-speed sweep block frame shift block high-speed sweep block frame shift block 135 27 123 27 135 123 3 3 ? 30 ? CXD3423GA chart-a4 horizontal direction timing chart mode frame mode applicable ccd image sensor icx432 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3mhz). this chart shows a peri od of 104ck (4.3s). ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id and wen are output at the timing shown above at the position shown in chart-a1. ? clpob also has patterns of 14-38, 26-50 and 14-50 for a total of four patterns. clpob (wide) is output in the shaded portions s hown in chart-a1. these timings can be switched by the serial interface data. (2760) 0 100 200 300 400 500 600 700 672 676 680 52 5 800 900 1000 644 hd h1 mcko v1 h2 v2 v3a/b v4 v5a/b v6 sub pblk clpob wen/fld id/exp clpdm clpob (wide) 182 308 266 392 350 476 434 560 140 518 224 602 52 135 52 670 20 44 646 670 50 140 140 674 ? 31 ? CXD3423GA chart-a5 horizontal direction timing chart mode draft/af mode applicable ccd image sensor icx432 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3mhz). this chart shows a peri od of 104ck (4.3s). ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id and wen are output at the timing shown above at the position shown in chart-a2 and a3. ? clpob also has patterns of 14-38, 26-50 and 14-50 for a total of four patterns. clpob (wide) is output in the shaded portions s hown in chart-a2 and a3. these timings can be switched by the serial interface data. (3004) 0 100 200 300 400 500 600 700 916 924 52 5 800 900 1000 888 920 hd h1 mcko v1 h2 v2 v3a/b v4 v5a/b v6 sub pblk clpob wen/fld id/exp clpdm clpob (wide) 171 264 543 636 233 326 605 698 295 388 667 760 357 450 729 822 419 512 140 791 481 574 202 853 52 135 52 914 20 44 890 914 50 140 140 918 ? 32 ? CXD3423GA chart-a6 horizontal direction timing chart (high-speed sweep: d) mode frame mode applicable ccd image sensor icx432 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3mhz). this chart shows a peri od of 104ck (4.3s). (2760) 0 100 200 (2760) 0 100 200 300 400 52 5 52 5 #1 #2 #3 #1039 #1040 hd h1 mcko v1 h2 v2 v3a/b v4 v5a/b v6 sub pblk clpob wen/fld id/exp clpdm 52 135 52 135 140 176 248 284 356 392 1952 1988 182 2060 158 194 266 302 374 410 1970 2006 176 212 284 320 392 428 1988 2024 194 230 302 338 410 446 2006 2042 212 248 320 356 428 2024 1952 140 230 266 338 374 446 1970 2042 224 140 158 ? 33 ? CXD3423GA chart-a7 horizontal direction timing chart (frame shift: f) mode af mode applicable ccd image sensor icx432 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3mhz). this chart shows a peri od of 104ck (4.3s). ? sub is output at the timing shown above when output is controlled by the serial interface data. ? frame shift of v1, v2, v3a/b, v4, v5a/b and v6 is performed up to 24h 1096ck (#78). (3004) 0 100 200 300 400 500 600 700 916 924 52 5 800 900 1000 888 920 hd h1 mcko v1 h2 v2 v3a/b v4 v5a/b v6 sub pblk clpob wen/fld id/exp clpdm 171 264 543 636 915 1008 233 326 605 698 977 295 388 667 760 1039 357 450 729 822 419 512 791 884 481 574 202 853 946 52 135 #1 #2 140 ? 34 ? CXD3423GA chart-a8 horizontal direction timing chart (high-speed sweep: g) mode af mode applicable ccd image sensor icx432 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3mhz). this chart shows a peri od of 104ck (4.3s). ? sub is output at the timing shown above when output is controlled by the serial interface data. ? high-speed sweep of v1, v2, v3a/b, v4, v5a/b and v6 is performed up to 133h 2932ck (#114). (3004) 0 100 200 300 400 500 600 700 916 924 52 5 800 900 1000 888 920 hd h1 mcko v1 h2 v2 v3a/b v4 v5a/b v6 sub pblk clpob wen/fld id/exp clpdm 152 188 296 332 440 476 584 620 728 764 872 908 1016 1052 176 212 320 356 464 500 608 644 752 788 896 932 1040 200 236 344 380 488 524 632 668 776 812 920 956 224 260 368 404 512 548 656 692 800 836 944 980 248 284 392 428 536 572 680 716 824 860 968 1004 140 272 308 416 452 560 596 704 740 848 884 992 1028 164 52 135 #1 #2 #3 140 ? 35 ? CXD3423GA chart-a9ahorizontal direction timing chart mode frame mode applicable ccd image sensor icx432 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3mhz). this chart shows a peri od of 104ck (4.3s). (2760) 0 (2760) 0 1254 1296 1338 1380 1420 1460 1502 1546 140 182 224 266 308 350 392 434 476 518 560 602 hd v1 v2 v3a/b v4 v5a/b v6 v1 b field a field [b] [a] v2 v3a/b v4 v5a/b v6 ? 36 ? CXD3423GA chart-a9b horizontal direction timing chart mode frame mode applicable ccd image sensor icx432 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3mhz). this chart shows a peri od of 104ck (4.3s). (2760) 0 (2760) 0 1086 1128 1170 1212 1254 1296 1338 1380 1420 1460 140 182 224 266 308 350 392 434 476 518 560 602 hd v1 v2 v3a/b v4 v5a/b v6 c field [c] ? 37 ? CXD3423GA chart-a10horizontal direction timing chart mode draft/af mode applicable ccd image sensor icx432 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 2.2 to 26.5s (when the drive frequency is 24.3mhz). this chart shows a peri od of 104ck (4.3s). (3004) 0 1407 1438 1469 1500 1540 1580 1611 1642 1673 1704 1744 1784 1815 1846 1877 1908 (3004) 0 140 171 202 233 264 295 326 357 388 419 450 481 512 543 574 605 636 667 698 729 hd v1 v2 v3a v3b v4 v5a [e] v5b v6 ? 38 ? CXD3423GA chart-a11vertical direction sequence chart mode draft frame draft applicable ccd image sensor icx432 ? this chart is a driving timing chart example of electronic shutter normal operation. ? data exposed at b includes a blooming component. for details, see the ccd image sensor data sheet. ? the CXD3423GA does not generate the pulse to control mechanical shutter operation. ? the drive mode and the electronic shutter data are not switched at the same timing. ccd out sub vd mechanical shutter 000 mode 000 000 010 010 010 000 000 a b c (1st) close c (2nd) c (3rd) open d 1 smd 1 1 0 0 0 1 1 050h shr 050h 050h 000h 000h 000h 050h 050h a d b c v1 v2 v3a v3b v4 v5a v5b v6 ? 39 ? CXD3423GA chart-b1 vertical direction timing chart mode frame mode applicable ccd image sensor icx434 ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. in this drive mode, id is reset to (high, low) in the horizontal periods of each readout portion (a, b). ? wen/fld of this chart shows wen. ? vd of this chart is indicated in ntsc equivalent pattern 650h (1h: 1848ck) units. for pal equivalent pattern, it is 779h + 408c k units. ? this chart shows the pin configuration for the icx434. (see page 3.) [a] [c] 1 1 [b] high-speed sweep block high-speed sweep block b field a field [c] 1228 1230 1232 1234 1236 3 1 5 7 9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 1227 1225 1229 1231 1233 1235 2 4 6 8 10 2 4 6 8 10 12 vd sub hd v1a v1b v2 v3a v3b v4 ccd out pblk clpob wen/fld id/exp clpdm 650 650 25 31 24 31 ? 40 ? CXD3423GA chart-b2 vertical direction timing chart mode draft mode applicable ccd image sensor icx434 ? the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. ? id/exp of this chart shows id. id is low for lines where ccd out contains the r component, and high for lines where ccd out con tains the b component. in this drive mode, id is reset to high in the horizontal periods of each readout portion (d). ? wen/fld of this chart shows wen. ? vd of this chart is indicated in ntsc equivalent pattern 325h (1h: 1848ck) units. for pal equivalent pattern, it is 389h + 1128 ck units. ? this chart shows the pin configuration for the icx434. (see page 3.) [d] 1 1 [d] 1207 1210 1215 1218 1223 1226 1231 1234 4 9 2 7 10 15 18 23 26 31 34 39 42 47 50 55 58 63 1207 1202 1210 1215 1218 1223 1226 1231 1234 4 9 2 7 10 15 18 23 26 31 34 vd sub hd v1a v1b v2 v3a v3b v4 ccd out pblk clpob wen/fld id/exp clpdm 325 325 12 16 12 16 ? 41 ? CXD3423GA chart-b3 horizontal direction timing chart mode frame mode applicable ccd image sensor icx434 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18mhz). this chart shows a period of 104ck (5.8s). ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id and wen are output at the timing shown above at the position shown in chart-b1. ? clpob also has patterns of 13-39, 25-51 and 13-51 for a total of four patterns. clpob (wide) is output in the shaded portions s hown in chart-b1. these timings can be switched by the serial interface data. ? this chart shows the pin configuration for the icx434. (see page 3.) (1848) 0 50 100 150 200 250 188 56 hd h1 mcko v1a/b h2 v2 v3a/b v4 sub pblk clpob clpob (wide) clpdm wen/fld id/exp 72 120 104 152 136 56 88 152 88 168 56 214 19 45 51 216 190 214 104 104 ? 42 ? CXD3423GA chart-b4 horizontal direction timing chart mode draft mode applicable ccd image sensor icx434 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18mhz). this chart shows a period of 104ck (5.8s). ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id and wen are output at the timing shown above at the position shown in chart-b2. ? clpob also has patterns of 13-39, 25-51 and 13-51 for a total of four patterns. clpob (wide) is output in the shaded portions s hown in chart-b2. these timings can be switched by the serial interface data. ? this chart shows the pin configuration for the icx434. (see page 3.) (1848) 0 50 100 150 200 250 188 hd h1 mcko v1a/b h2 v2 v3a/b v4 sub pblk clpob clpob (wide) clpdm wen/fld id/exp 56 56 88 120 152 72 104 136 168 88 120 56 152 88 152 104 136 72 168 56 214 19 45 51 216 190 214 104 104 ? 43 ? CXD3423GA chart-b5 horizontal direction timing chart (high-speed sweep: c) mode frame mode applicable ccd image sensor icx434 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.1 to 10.4s (when the drive frequency is 18mhz). this chart shows a period of 104ck (5.8s). ? sub is output at the timing shown above when output is controlled by the serial interface data. ? id and wen are output at the timing shown above at the position shown in chart-b1. ? high-speed sweep of v1a/b, v2, v3a/b and v4 is performed up to 22h 1848ck (#758). ? this chart shows the pin configuration for the icx434. (see page 3.) #1 #3 (1848) 0 50 100 150 200 250 188 hd h1 mcko v1a/b h2 v2 v3a/b v4 sub pblk clpob clpdm wen/fld id/exp 88 152 56 56 84 112 140 168 196 224 252 70 98 126 154 182 210 238 266 70 98 126 154 182 210 238 266 56 84 112 140 168 196 224 252 #2 #4 ? 44 ? CXD3423GA chart-b6 horizontal direction timing chart mode frame mode applicable ccd image sensor icx434 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximately 3.0 to 13.4s (when the drive frequency is 18mhz). this chart shows a period of 104ck (5.8s). ? this chart shows the pin configuration for the icx434. (see page 3.) (1848) 0 56 72 88 104 120 136 152 168 184 200 216 (1848) 0 56 72 88 104 120 136 152 168 1027 1029 1071 1091 1131 1133 1175 logical alignment hd v1a v1b v2 v3a v3b v4 v1a b field a field [b] [a] v1b v2 v3a v3b v4 ? 45 ? CXD3423GA chart-b7 horizontal direction timing chart mode draft mode applicable ccd image sensor icx434 ? hd of this chart indicates the actual CXD3423GA load timing. ? the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hd. ? the hd fall period should be between approximates (when the drive frequency is 18mhz). this chart shows a period of 104ck (5.8 s). ? this chart shows the pin configuration for the icx434. (see page 3.) (1848) 0 56 72 88 104 120 136 152 168 (1848) 0 56 72 88 104 120 136 152 168 1027 1029 1071 1091 1131 1111 1133 1175 hd v1a v1b v2 v3a v3b v4 [d] ? 46 ? CXD3423GA chart-b8 vertical direction sequence chart mode draft frame draft applicable ccd image sensor icx434 ? this chart is a driving timing chart example of electronic shutter normal operation. ? data exposed at d includes a blooming component. for details, see the ccd image sensor data sheet. ? the CXD3423GA does not generate the pulse to control mechanical shutter operation. ? the drive mode and the electronic shutter data are not switched at the same timing. ? this chart shows the pin configuration for the icx434. (see page 3.) ccd out sub vd mechanical shutter 050h shr 050h 050h 000 1 050h 000 1 050h 050h 050h 050h 050h a f b c d e 000 mode 000 000 010 000 000 abcd close ee open f 010 1 smd 1 1 0 0 1 1 v1a v1b v2 v3a v3b v4 ? 47 ? CXD3423GA chart-z high-speed phase timing chart mode applicable ccd image sensor icx432/icx434 ? hd' indicates the hd which is the actual CXD3423GA load timing. ? the phase relationship of each pulse shows the logical position relationship. for the actual output waveform, a delay is added to each pulse. ? the logical phase of adclk can be specified by the serial interface data. cki hd' hd cko rg xshd xshp adclk mcko h1 1 h2 56/52 188/644/888 ? 48 ? CXD3423GA ccd signal processor block serial interface control the CXD3423GA's ccd signal processor block basically loads the ccd signal processor block serial interface data sent in the following format at the rising edge of sen2, and the setting values are then reflected to the operation 6 adclki clocks after that. ccd signal processor block serial interface control requires clock input to adclki in order to load and reflect the serial interface data to operation, so this should normally be performed when the timing generator block is in the normal operation mode. there are five categories of ccd signal processor block serial interface data: standby control data, pga gain setting data, ob clamp level setting data, input pulse polarity setting data, and output delay adjustment data. note that when data from multiple categories is loaded consecutively, the data for the category loaded last is valid and data from other categories is lost. when transferring data from multiple categories, raise sen2 for each category and wait until the setting value has been reflected to operation 6 adckli clocks after that, then transmit the next category. when the power supply is set to on, be sure to initialize for transmitting all category data. the details of each data are described below. standby control data data d00 d01 to d03 d04 to d14 d15 symbol test ctg fixed stb function test code category switching ? standby control data = 0 data = 1 standby mode normal operation mode set to "0". d01 to d03 ctg set to "all 0". data d00 d01 to d03 d04, d05 d06 to d15 symbol test ctg fixed gain function test code category switching ? pga gain setting data data = 0 data = 1 set to "0". d01 to d03 ctg set to "all 0". see d06 to d15 gain. pga gain setting data 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 ssi2 sck2 sen2 ? 49 ? CXD3423GA data d00 d01 to d03 d04 to d11 d12 to d15 symbol test ctg fixed oblvl function test code category switching ? ob clamp level setting data data = 0 data = 1 set to "0". d01 to d03 ctg set to "all 0". see d12 to d15 oblvl. ob clamp level setting data data d00 d01 to d03 d04 to d12 d13 to d15 symbol test ctg fixed pol function test code category switching ? input pulse polarity setting data data = 0 data = 1 set to "0". d01 to d03 ctg set to "all 0". set to "all 0". input pulse polarity setting data output delay adjustment data data d00 d01 to d03 d04 to d13 d14, d15 symbol test ctg fixed odl function test code category switching ? output delay adjustment data data = 0 data = 1 set to "0". d01 to d03 ctg set to "all 0". see d14 and d15 odl. ? 50 ? CXD3423GA detailed description of each data shared data: d01 to d03 ctg [category] of the data provided to the CXD3423GA by the ccd signal processor block serial interface, the CXD3423GA loads d04 and subsequent data to each data register as shown in the table below according to the combination of d01 to d03 . standby control data: d15 stb [standby] the operating mode of the ccd signal processor block is switched as follows. when the ccd signal processor block is in standby mode, only the serial interface is valid. pga gain setting data: d06 to d15 gain [pga gain] the CXD3423GA can set the programmable gain amplifier (pga) gain from ?6db to +42db in 1024 steps by using pga gain setting data d06 to d15 gain. the pga gain setting data is expressed as shown in the table below using d06 to d15 gain. for example, when gain is set to "000h", "080h", "220h", "348h" and "3ffh", the respective pga gain setting values are ?6db, 0db, +20db, +34db and +42db. msb d06 0 d07 1 d08 1 d09 1 d10 0 d11 0 d12 0 d13 0 d14 1 d15 1 lsb 1 c 3 gain is expressed as 1c3h . d15 0 1 description of operation normal operating mode standby mode d01 0 0 0 0 1 1 1 d02 0 0 1 1 0 0 1 description of operation loading to standby control data register loading to pga gain setting data register loading to ob clamp level setting data register loading to input pulse polarity setting data register loading to output delay adjustment data register access prohibited access prohibited d03 0 1 0 1 0 1 x ? 51 ? CXD3423GA ob clamp level setting data: d12 to d15 oblvl [ob clamp level] the CXD3423GA can set the opb clamp output value from 0 to 60lsb in 4lsb steps by using ccd signal processor block control data d12 to d15 oblvl. the opb clamp output setting data is expressed as shown in the table below using d12 to d15 oblvl. for example, when oblvl is set to "0h", "1h", "8h" and "fh", the respective opb clamp output setting values are 2lsb, 18lsb, 130lsb and 242lsb. d12 0 d13 1 d14 1 d15 0 lsb 6 oblvl is expressed as 6h . msb output delay adjustment data: d14 and d15 odl [output delay] the CXD3423GA can adjust the output delay time of 12-bit digital output against rising of adclk by using output delay adjustment data d14 and d15 odl. d14 0 0 1 1 description of operation output delay is not added. output delay addition 5ns (typ.) output delay addition 10ns (typ.) output delay addition 13ns (typ.) d15 0 1 0 1 note: in the case that the output delay is not added, the delay time is about 2 to 10ns. ? 52 ? CXD3423GA application circuit block diagram this is the block diagram indicating the connection relations between this ic and each circuit block, and not the actual circui t diagram. regarding the concrete connection circuit example with the ccd image sensor, see the data sheet of the ccd image sensor. application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same . sen2 sck2 ssi2 f9 f8 f7 g2 g3 g9 g8 g7 h2 h1 g1 b7 a7 c6 b3 a1 a2 b2 b1 c3 c2 c1 d3 d2 d1 e1 j2 k2 m2 n2 n9 m9 m8 n8 l8 m4 m5 n4 k8 j9 j8 c8 c7 d8 d7 c9 n5 l4 n7 m7 a3 b4 a4 m1 n1 l2 b5 c4 l1 j1 k1 a5 l3 h7 h3 ccd icx284/icx432/icx434 tg/cds/pga/adc CXD3423GA controller ssi1 sen1 sck1 test5 test4 test3 test2 test1 osco cki osci d3 vd hd d2 signal processor block d4 d5 d6 d7 d8 d9 d10 d11 (msb) mcko cko ssgsl sncsl rst wen/fld id/exp 0.1f c7 xshpi xshdi pblki clpdmi clpobi xshp xshd pblk clpdm clpob adclk adclki 0.1f c8 0.1f c9 1f c1 1f ccdin ccdout 390pf c2 390pf c3 240pf c4 h1 h2 rg v5a v5b v2 n6 v3b l6 v3a v4 sub v1 v6 d0 (lsb) d1 ? 53 ? CXD3423GA notes on operation 1. be sure to start up the timing generator block vl and vh pin power supplies at the timing shown in the figure below in order to prevent the sub pin of the ccd image sensor from going to negative potential. in addition, start up the timing generator block v dd1 , v dd2 , v dd3 , v dd4 and v dd5 pins and ccd signal processor block dv dd1 , dv dd2 , av dd1 , av dd2 , av dd3 , av dd4 and av dd5 pin power supplies at the same time either before or at the same time as the vh pin power supply is started up. 2. reset the timing generator block and ccd signal processor block during power-on. the timing generator block is reset by inputting the reset signal to the rst pin. the ccd signal processor block is reset by initializing the serial data. 3. separate the timing generator block v dd1 , v dd2 , v dd3 , v dd4 and v dd5 pins from the ccd signal processor block dv dd1 , dv dd2 , av dd1 , av dd2 , av dd3 , av dd4 , and av dd5 pins. also, the adc output driver stage is connected to the dedicated power supply pin dv dd1 . separating this pin from other power supplies is recommended to avoid affecting the internal analog circuits. 4. the difference in potential between the timing generator block v dd4 , pin supply voltage 3 v dd c and the ccd signal processor block dv dd1 , dv dd2 , av dd1 , av dd2 , av dd3 , av dd4 and av dd5 pin supply voltages 1 v dd e, 2 v dd f and 3 v dd g should be 0.1v or less. 5. the timing generator block and ccd signal processor block ground pins should use a shared ground which is connected outside the ic. when the set ground is divided into digital and analog blocks, connect the timing generator block ground pins to the dig ital ground and the ccd signal processor block ground pins to the analog ground. the difference in potential between the timing generator block v ss1 , v ss2 , v ss3 , v ss4 , v ss5 and vm and the ccd signal processor block dv ss1 , dv ss2 , dv ss3 , av ss1 , av ss2 , av ss3 , av ss4 , av ss5 and av ss6 should be 0.1v or less. 6. do not perform serial communication with the ccd signal processor block during the effective image period, as this may cause the picture quality to deteriorate. in addition, using sck2, ssi2 and sen2, which are used by the ccd signal processor block, use of the dedicated ports is recommended. when using these pins as shared ports with the timing generator block or other ics, be sure to thoroughly confirm the effects on picture quality before use. t1 t2 +15.0v 0v ?7.5v 20% 20% t2 t1 ? 54 ? CXD3423GA sony corporation package outline unit: mm 96pin lflga package mass package structure organic substrate 0.3g package material terminal treatment terminal material sony code eiaj code jedec code lflga-96p-02 p-lflga96-12x8-0.8 1.3 max s 0.10 detail x s s 0.2 pin 1 index x b b 0.2 12.0 s 8.0 a 0.2 s 0.15 x4 0.8 b d e f g h j k l c a m n 123456789 0.8 m sab 96 - 0.45 0.05 a 0.5 0.5 3 ? 0.50 0.5 0.9 0.9 1.2 0.8 0.10max 0.5 0.08 (0.3) (0.3) (0.3) (0.3) nickel & gold plating copper |
Price & Availability of CXD3423GA
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |